Macros
#define	ADXL_CMD_WRITE_REG 0x0A

#define	ADXL_CMD_READ_REG 0x0B

#define	ADXL_CMD_READ_FIFO 0x0D

#define	ADXL_REG_DEVID_AD 0x00

#define	ADXL_REG_DEVID_MST 0x01

#define	ADXL_REG_PARTID 0x02

#define	ADXL_REG_REVID 0x03

#define	ADXL_REG_XDATA 0x08

#define	ADXL_REG_YDATA 0x09

#define	ADXL_REG_ZDATA 0x0A

#define	ADXL_REG_STATUS 0x0B

#define	ADXL_REG_FIFO_ENTRIES_L 0x0C

#define	ADXL_REG_FIFO_ENTRIES_H 0x0D

#define	ADXL_REG_XDATA_L 0x0E

#define	ADXL_REG_XDATA_H 0x0F

#define	ADXL_REG_YDATA_L 0x10

#define	ADXL_REG_YDATA_H 0x11

#define	ADXL_REG_ZDATA_L 0x12

#define	ADXL_REG_ZDATA_H 0x13

#define	ADXL_REG_TEMP_L 0x14

#define	ADXL_REG_TEMP_H 0x15

#define	ADXL_REG_Reserved0 0x16

#define	ADXL_REG_Reserved1 0x17

#define	ADXL_REG_SOFT_RESET 0x1F

#define	ADXL_REG_THRESH_ACT_L 0x20

#define	ADXL_REG_THRESH_ACT_H 0x21

#define	ADXL_REG_TIME_ACT 0x22

#define	ADXL_REG_THRESH_INACT_L 0x23

#define	ADXL_REG_THRESH_INACT_H 0x24

#define	ADXL_REG_TIME_INACT_L 0x25

#define	ADXL_REG_TIME_INACT_H 0x26

#define	ADXL_REG_ACT_INACT_CTL 0x27

#define	ADXL_REG_FIFO_CONTROL 0x28

#define	ADXL_REG_FIFO_SAMPLES 0x29

#define	ADXL_REG_INTMAP1 0x2A

#define	ADXL_REG_INTMAP2 0x2B

#define	ADXL_REG_FILTER_CTL 0x2C

#define	ADXL_REG_POWER_CTL 0x2D

#define	ADXL_REG_SELF_TEST 0x2E

Macro Definition Documentation

◆ ADXL_CMD_READ_FIFO

#define ADXL_CMD_READ_FIFO 0x0D

◆ ADXL_CMD_READ_REG

#define ADXL_CMD_READ_REG 0x0B

◆ ADXL_CMD_WRITE_REG

#define ADXL_CMD_WRITE_REG 0x0A

accel_registers.h

Register map for the ADXL362 digital accelerometer

Date: Aug 2013

Author: Aaron Parks

◆ ADXL_REG_ACT_INACT_CTL

#define ADXL_REG_ACT_INACT_CTL 0x27

◆ ADXL_REG_DEVID_AD

#define ADXL_REG_DEVID_AD 0x00

◆ ADXL_REG_DEVID_MST

#define ADXL_REG_DEVID_MST 0x01

◆ ADXL_REG_FIFO_CONTROL

#define ADXL_REG_FIFO_CONTROL 0x28

◆ ADXL_REG_FIFO_ENTRIES_H

#define ADXL_REG_FIFO_ENTRIES_H 0x0D

◆ ADXL_REG_FIFO_ENTRIES_L

#define ADXL_REG_FIFO_ENTRIES_L 0x0C

◆ ADXL_REG_FIFO_SAMPLES

#define ADXL_REG_FIFO_SAMPLES 0x29

◆ ADXL_REG_FILTER_CTL

#define ADXL_REG_FILTER_CTL 0x2C

◆ ADXL_REG_INTMAP1

#define ADXL_REG_INTMAP1 0x2A

◆ ADXL_REG_INTMAP2

#define ADXL_REG_INTMAP2 0x2B

◆ ADXL_REG_PARTID

#define ADXL_REG_PARTID 0x02

◆ ADXL_REG_POWER_CTL

#define ADXL_REG_POWER_CTL 0x2D

◆ ADXL_REG_Reserved0

#define ADXL_REG_Reserved0 0x16

◆ ADXL_REG_Reserved1

#define ADXL_REG_Reserved1 0x17

◆ ADXL_REG_REVID

#define ADXL_REG_REVID 0x03

◆ ADXL_REG_SELF_TEST

#define ADXL_REG_SELF_TEST 0x2E

◆ ADXL_REG_SOFT_RESET

#define ADXL_REG_SOFT_RESET 0x1F

◆ ADXL_REG_STATUS

#define ADXL_REG_STATUS 0x0B

◆ ADXL_REG_TEMP_H

#define ADXL_REG_TEMP_H 0x15

◆ ADXL_REG_TEMP_L

#define ADXL_REG_TEMP_L 0x14

◆ ADXL_REG_THRESH_ACT_H

#define ADXL_REG_THRESH_ACT_H 0x21

◆ ADXL_REG_THRESH_ACT_L

#define ADXL_REG_THRESH_ACT_L 0x20

◆ ADXL_REG_THRESH_INACT_H

#define ADXL_REG_THRESH_INACT_H 0x24

◆ ADXL_REG_THRESH_INACT_L

#define ADXL_REG_THRESH_INACT_L 0x23

◆ ADXL_REG_TIME_ACT

#define ADXL_REG_TIME_ACT 0x22

◆ ADXL_REG_TIME_INACT_H

#define ADXL_REG_TIME_INACT_H 0x26

◆ ADXL_REG_TIME_INACT_L

#define ADXL_REG_TIME_INACT_L 0x25

◆ ADXL_REG_XDATA

#define ADXL_REG_XDATA 0x08

◆ ADXL_REG_XDATA_H

#define ADXL_REG_XDATA_H 0x0F

◆ ADXL_REG_XDATA_L

#define ADXL_REG_XDATA_L 0x0E

◆ ADXL_REG_YDATA

#define ADXL_REG_YDATA 0x09

◆ ADXL_REG_YDATA_H

#define ADXL_REG_YDATA_H 0x11

◆ ADXL_REG_YDATA_L

#define ADXL_REG_YDATA_L 0x10

◆ ADXL_REG_ZDATA

#define ADXL_REG_ZDATA 0x0A

◆ ADXL_REG_ZDATA_H

#define ADXL_REG_ZDATA_H 0x13

◆ ADXL_REG_ZDATA_L

#define ADXL_REG_ZDATA_L 0x12

Macros