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| uint8_t const | ADXL_READ_PARTID [] = {ADXL_CMD_READ_REG,ADXL_REG_PARTID,0x00} |
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| uint8_t const | ADXL_READ_DEVID [] = {ADXL_CMD_READ_REG,ADXL_REG_DEVID_AD,0x00} |
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| uint8_t const | ADXL_REAsxD_STATUS [] = {ADXL_CMD_READ_REG,ADXL_REG_STATUS,0x00} |
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| uint8_t const | ADXL_READ_XYZ_8BIT [] = {ADXL_CMD_READ_REG,ADXL_REG_XDATA,0x00,0x00,0x00} |
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| uint8_t const | ADXL_READ_XYZ_16BIT [] = {ADXL_CMD_READ_REG,ADXL_REG_XDATA_L,0x00,0x00,0x00,0x00,0x00,0x00} |
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| uint8_t const | ADXL_READ_XYZ_16BIT_FIFO [] = {ADXL_CMD_READ_FIFO,0x00,0x00,0x00,0x00,0x00,0x00} |
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| uint8_t const | ADXL_CONFIG_MEAS [] = {ADXL_CMD_WRITE_REG,ADXL_REG_POWER_CTL,0x22} |
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| uint8_t const | ADXL_CONFIG_STBY [] = {ADXL_CMD_WRITE_REG,ADXL_REG_POWER_CTL,0x00} |
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| uint8_t const | ADXL_CONFIG_RESET [] = {ADXL_CMD_WRITE_REG,ADXL_REG_SOFT_RESET,0x52} |
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| uint8_t const | ADXL_CONFIG_FILTER [] = {ADXL_CMD_WRITE_REG,ADXL_REG_FILTER_CTL,0x14} |
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| uint8_t const | ADXL_CONFIG_INTERRUPT [] = {ADXL_CMD_WRITE_REG,ADXL_REG_INTMAP1,0X01} |
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| uint8_t const | ADXL_CONFIG_FIFO_CTL [] = {ADXL_CMD_WRITE_REG,ADXL_REG_FIFO_CONTROL,0X0A} |
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| uint8_t const | ADXL_CONFIG_FIFO_SAMPLE [] = {ADXL_CMD_WRITE_REG,ADXL_REG_FIFO_SAMPLES,6} |
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